Unité centrale de processeur (CPU) HCS08 8 bits
• 40-MHz HCS08 CPU (20-MHz bus)
• HC08 instruction set with added BGND instruction
• Support for up to 32 interrupt/reset sources

Mémoire sur puce
• FLASH read/program/erase over full operating voltage and temperature
• EEPROM in-circuit programmable memory; 8-byte single-page or 4-byte dual-page erase sector; Program and Erase while executing FLASH; Erase abort
• Random-access memory (RAM)

Modes d’économie d’énergie
• Two very low power stop modes
• Reduced power wait mode
• Very low power real time interrupt for use in run, wait, and stop

Options de source d’horloge
• Oscillator (XOSC) — Loop-control Pierce oscillator; Crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz
• Multi-purpose Clock Generator (MCG) — PLL and FLL modes; reference clock with nonvolatile trim (0.2% resolution, 1.5% tolerance over temperature with internal temperature compensation); External reference with oscillator/resonator options

Protection du système
• Watchdog computer operating properly (COP) reset with option to run from backup dedicated 1-kHz internal clock source or bus clock; with optional windowed operation
• Low-voltage detection with reset or interrupt; selectable trip points
• Illegal opcode detection with reset
• Illegal address detection with reset
• FLASH and EEPROM block protect
• Loss-of-lock protection

Soutien au développement
• Single-wire background debug interface
• On-chip, in-circuit emulation (ICE) with real-time bus capture

Entrée/Sortie
• Up to 87 general-purpose input/output (I/O) pins and 1 input-only pin
• Up to 32 interrupt pins with selectable polarity on each pin
• Hysteresis and configurable pull device on all input pins.
• Configurable slew rate and drive strength on all output pins.

Options de forfait
• 100-pin low-profile quad flat-pack(LQFP) — 14x14 mm
• 64-pin low-profile quad flat-pack (LQFP) — 10x10 mm
• 48-pin low-profile quad flat-pack (LQFP) — 7x7 mm