MCIMX6S1AVM08AC NXP
Available
MCIMX6S1AVM08AC NXP
• The i.MX 6Solo supports single Arm Cortex-A9 MPCore (with TrustZone)
• The i.MX 6DualLite supports dual Arm Cortex-A9 MPCore (with TrustZone)
• The core configuration is symmetric, where each core includes:
— 32 KByte L1 Instruction Cache
— 32 KByte L1 Data Cache
— Private Timer and Watchdog
— Cortex-A9 NEON MPE (Media Processing Engine) Co-processor
• General Interrupt Controller (GIC) with 128 interrupt support
• Global Timer
• Snoop Control Unit (SCU)
• 512 KB unified I/D L2 cache:
— Used by one core in i.MX 6Solo
— Shared by two cores in i.MX 6DualLite
• Two Master AXI bus interfaces output of L2 cache
• Frequency of the core (including NEON and L1 cache), as per Table 8.
• NEON MPE coprocessor
— SIMD Media Processing Architecture
— NEON register file with 32x64-bit general-purpose registers
— NEON Integer execute pipeline (ALU, Shift, MAC)
— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
— NEON load/store and permute pipeline
• The i.MX 6Solo supports single Arm Cortex-A9 MPCore (with TrustZone)
• The i.MX 6DualLite supports dual Arm Cortex-A9 MPCore (with TrustZone)
• The core configuration is symmetric, where each core includes:
— 32 KByte L1 Instruction Cache
— 32 KByte L1 Data Cache
— Private Timer and Watchdog
— Cortex-A9 NEON MPE (Media Processing Engine) Co-processor
• General Interrupt Controller (GIC) with 128 interrupt support
• Global Timer
• Snoop Control Unit (SCU)
• 512 KB unified I/D L2 cache:
— Used by one core in i.MX 6Solo
— Shared by two cores in i.MX 6DualLite
• Two Master AXI bus interfaces output of L2 cache
• Frequency of the core (including NEON and L1 cache), as per Table 8.
• NEON MPE coprocessor
— SIMD Media Processing Architecture
— NEON register file with 32x64-bit general-purpose registers
— NEON Integer execute pipeline (ALU, Shift, MAC)
— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
— NEON load/store and permute pipeline
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